Asic Design Verification Engineer (Sr Staff/Principal)

Detalles de la oferta

Description Company Summary: Join our talented team at ForwardEdge ASIC, an industry leading ASIC design company. We are committed to pushing the boundaries of technology through cutting-edge ASIC designs that redefine industry standards. As an ASIC Design Verification Engineer, you will play a pivotal role in ensuring the robustness and reliability of our ASIC products, contributing to our mission of delivering superior solutions to our customers.

Job Overview: We are seeking a highly skilled Sr. Staff/Principal ASIC Design Verification Engineer to lead our verification efforts across complex ASIC and FPGA designs. In this role, you will be responsible for driving the verification strategy, methodologies, and implementation from inception to delivery. Your expertise will be crucial in ensuring that our ASIC designs meet functional and performance requirements while adhering to high standards of quality and reliability.

Key Responsibilities: Lead the verification team in planning, developing, and executing verification strategies for ASIC and FPGA designs. Define verification methodologies, verification plans, and environments to ensure comprehensive verification coverage. Collaborate closely with architects, design, and analog teams to understand design specifications and develop efficient verification strategies. Drive the development of verification components, including test benches, test cases, and assertion-based verification IP. Conduct complex debugging and root cause analysis of verification failures to ensure timely resolution. Mentor and guide junior verification engineers, providing technical leadership and fostering a culture of innovation and excellence. Stay updated with industry trends, tools, and methodologies in verification to continually improve our capabilities. Qualifications: Bachelor's in electrical engineering, computer Engineering, or related field. Proven experience (typically 10+ years) in ASIC design verification, with a strong understanding of verification methodologies such as UVM and SystemVerilog. Hands-on experience in developing verification environments and test benches for complex ASIC designs. Expertise in scripting languages such as Python for automation and efficiency. Proficiency in industry-standard EDA tools for simulation, debug, and verification closure. Excellent problem-solving skills and the ability to analyze and debug complex verification issues. Strong leadership skills with experience in leading or mentoring a team of verification engineers. Effective communication skills and the ability to collaborate effectively with cross-functional teams. Clearance: This position requires a US government security clearance. As such, US citizenship is required. Nice to Have: Master's degree in computer engineering, electrical engineering, or a related field. Experience in verification of high-speed interfaces (e.g., PCIe, DDR, UCIe), AI/ML, complex data processing, and/or processor-based designs. Familiarity with formal verification techniques and tools. Knowledge of FPGA prototyping and emulation platforms. Experience with verification of ASICs targeting AI/ML, networking, or automotive applications. Work Environment: The work environment for this role typically involves a combination of office-based activities and collaboration with analog design, CAD, and physical verification teams. Occasional travel may be required for project meetings or customer engagements.

Benefits: Work-life balance: Flexible 9/80 Work schedules with every other Friday off, hybrid work with primary location being in St. Paul, MN Competitive benefit package: Including options for healthcare and medical coverage, 401K Retirement Benefits with company contribution, as well as a generous holidays and PTO allotment. Selected candidate may also be eligible for short-term and long-term incentives. Join us at ForwardEdge ASIC and be part of a team that thrives on innovation and excellence in ASIC design verification. Together, we'll shape the future of technology.

*Please note that this role is for Sr Staff or Principal Engineer, depending on qualifications.

Pay Range

$150,000.00 None to $200,000.00 None


Salario Nominal: A convenir

Fuente: Appcast_Ppc

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